1. Field of The Invention
The present invention relates to digital test systems of the type in which digital signals which are present within electrical circuits under test are monitored and tested to determine if they qualify as a logic level expected to result from predetermined digital tests and, particularly, to a digital comparator for determining if the level of a digital test signal qualifies as an expected logic level.
2. State of The Prior Art
It is quite common in digital test equipment to test the level of a digital signal in order to determine if the signal level meets certain preset standards and therefore qualifies as a particular logic level. In digital test equipment of the "in-circuit" type, for example, individual digital devices (e.g., integrated circuits) on a larger unit such as a printed circuit board are tested by providing access to all the necessary terminals of the devices and then exercising the devices in accordance with some predetermined functional routine.
In such a system, the devices are exercised by applying digital stimulus signals to appropriate terminals of the devices so that the devices produce resultant output signals. These output signals (hereinafter "test signals") are monitored and are tested to determine if they are indeed at a logic level expected to result from the test being performed and therefore if the devices are operating properly. The monitoring and testing procedure is usually carried out by digital comparators which use appropriate standards to first determine if the signal level of the test signal qualifies as one of a plurality of possible logic levels and secondly, if that signal level is the one logic level expected to result from the test.
Known digital comparators of the type described above ordinarily have a complete comparison and signal conditioning channel for each logic level which is permissible in the type of device being tested. Moreover, a logic circuit is also required to test the comparator results against an expected test result in order to ensure that the detected logic level is as expected. Thus, for example, for bistate or binary device testing there are two complete comparison and signal conditioning channels and a logic circuit associated with each digital comparator.
In addition, known digital comparators used for in-circuit testing have an input impedance which is fixed at a value calculated to maximize accuracy and speed for all types of tests that may be performed by the test system. This value obviously cannot be ideal for all types of tests since in most tests a relatively low impedance is required for maximum testing speed and accuracy, yet in other tests a relatively high input impedance is required.
Further, digital testers of the in-circuit type may have a large number of comparators (e.g., one for each pin of the test fixture). Only a relatively small number of these comparators are necessary at any instant during a test of a digital device on the unit under test yet all of the comparators are fully energized during each test in the sense that they are powered and are drawing supply current, although their outputs may be ignored at that instant.